Design and Implementation of Low Offset Sensor Interface for Differential Capacitive Sensors

Tirupathi, Rakesh (2021) Design and Implementation of Low Offset Sensor Interface for Differential Capacitive Sensors. PhD thesis.

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Nowadays, due to advancement of micro fabrication technology, Micro-Electro-Mechanical-Systems (MEMS) based miniature sensors are becoming more popular. But sensing physical variables, which are analog in nature, with these sensors is a challenging task. Among different type of MEMS based sensors, capacitive sensors are preferred for the measurement of displacement, pressure, acceleration etc. in various applications ranging from bio-medical devices to automotive safety. An integrated capacitive sensor system comprises of a capacitive sensor and a signal conditioning circuit, which provides electrical output as a function of change in capacitance (ΔC). These sensors offer several advantages such as smaller size, lower power consumption, higher sensitivity, lesser temperature coefficient and compatibility for monolithic integration. But due to micrometer dimension, these micro capacitive sensors provide very small change in capacitance, in the range of few femto-farad (fF). Detection of such small capacitance in the presence of considerable parasitics is quite challenging. Moreover, non-idealities of the interfacing circuit components, such as DC offset, 1/f noise, kT/C noise etc. limit the performance of the system. Chopper modulation, Auto-zeroing, Correlated Double Sampling etc. are quite popular to improve the performance of the interfacing circuit. In this work, we have proposed five switched capacitor based interfacing circuit topologies, which reduces the non ideal effects of the circuit components. Apart from these five configurations, we have also proposed an auto-calibration method to reduce the offset from sensor mismatch which can be implemented fully on-chip. These interfacing circuits are analysed theoretically and simulated using spectre simulator in Cadence Virtuoso environment. Among five interfacing circuits, four are designed and fabricated in UMC 180 nm CMOS process technology and the fifth one is designed in SCL 180 nm CMOS process technology. The fabricated UMC IC is integrated with a SOI MEMS capacitive acceleration sensor and measurement is carried out. Static characterization of the fabricated IC is carried out with the help of on-chip capacitors and the dynamic testing of the integrated system is done by a custom-made vibration setup with a sub-woofer system. The static and dynamic measurement results along with the merits and demerits of the proposed interfaces are reported in this thesis.

Item Type:Thesis (PhD)
Uncontrolled Keywords:ASIC; Calibration; Capacitive sensors; CMOS integrated circuits; FPGA; MEMS; Switched-capacitor circuits.
Subjects:Engineering and Technology > Electronics and Communication Engineering > Sensor Networks
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:10277
Deposited By:Mr. Sanat Kumar Behera
Deposited On:28 Apr 2022 10:28
Last Modified:28 Apr 2022 10:28
Supervisor(s):Kar, Sougata Kumar

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