Leakage Power Minimization in CMOS VLSI Circuits: Circuit level Approaches

Abstract

An electronic system/appliance/portable device with high speed, low power, and feasible area has become the finest choice for the consumer. CMOS technology has been continuously scaled down to meet the increasing demand of such kind. Nonetheless, the extent of scaling is constrained by physical limitations such as short-channel effects. The problem has taken a serious turn as the scaling extends into ultra-deep-submicron (UDSM) regime. The main consequences are the leakage currents contributing to massive static power dissipation. Hence the power dissipation has become the critical issue in the design of microelectronic circuits. These unsolicited leakage currents should be minimized for the smooth functioning of the circuit. Designing of such leakage free nanoscale CMOS circuits turns to be a challenging task. In this thesis, we have focused on the leakage power minimization of CMOS VLSI circuits. We have presented three proposed circuit level techniques to minimize the static power dissipation by controlling the subthreshold leakage current. Through exploiting the stacking effect, we have proposed a circuit level leakage reduction technique named LRT (Leakage Reluctant Transistor). Another novel circuit technique is proposed based on the source biasing approach. The third proposed technique works on the principle of increasing the effective resistance of the path from the supply voltage to ground. The design methodology for the implementation and the detailed analysis of the proposed techniques are presented in the thesis. Circuit simulations are carried out at three technology nodes: 90nm, 45nm, and 22nm. The detailed comparison of the performance parameters such as power dissipation, delay, power-delay product (PDP) of CMOS inverter, NAND gate, NOR gate and a benchmark circuit with the other reported techniques is presented. Simulation results show that the three proposed approaches achieves an average leakage power saving of 72 %, 31 %, and 74 % compared to the conventional design at 22nm technology node. However, the approaches increased the delay and area. Few of the proposed designs yields better power-delay product compared to conventional designs.