Architectural, Performance Exploration and Security Augmentation of Network on Chip

Abstract

The ever-increasing demand for portable and smart computing brought electronics design to a new paradigm, where a large number of electronic components can be integrated into a single chip to create a System on Chip (SoC). SoC integrates different cores, such as multi-processor, memory, input, and output peripheral cores, into a single chip. SoCs traditionally employ shared bus architecture for communicating between different cores. However, this provides certain limitations, such as reduced bandwidth along with unscalable architecture. To deal with these challenges and to increase communication efficiency between high-density components, Network on Chip (NoC) has been proposed as a viable solution. NoC is a subset of SoC that comprises different nodes connected via routers. Network interfaces (NIs) are used to connect core to routers in a network. The various parts of NoCs are routers, NIs, links, switches, buffers, allocators, and virtual channels. The communication between the cores occurs by sending the packets through the network. A routing algorithm is used to transfer messages from the source node to the destination node in a NoC. It plays a vital role in deciding the performance of the NoC. Finding an optimal solution to the shortest path between the source and the destination is always an active area for research. Hence, this work uses the Ant colony optimization (ACO) algorithm to propose a new routing algorithm that can be used to predict the shortest path between the source node and the destination node without compromising the performance of NoC. The results show the proposed algorithm reduces the latency of the NoC by 20 % in comparison to standard XY and Odd-even routing algorithms. Moreover, various architectural aspects of NoC design are considered. FPGA implementation of a 3x3 mesh NoC is done, and the parametrized resource evaluation is carried out. The throughput of an 8-bit flit width NoC is found to be 308.433 Mbps. The parameterized results will help the researcher to use this knowledge as a base work for designing NoC. Being a scalable and reliable commutation infrastructure, NoC is designed through various design stages that may lead to weaknesses in the system. Hence, the security aspect of NoC must be taken care of in the early stage of the SoC design. Being a communication architecture, NoC can handle security attacks and disallow undesired transactions by notifying components designed for security violations. Four types of Hardware Trojan(HT) called head Trojan, tail Trojan, address Trojan, and quantity Trojan, are designed and inserted in a 4x4 mesh NoC. As a result, the performance of NoC is degraded. A bit shuffling method has been proposed to mitigate the effect of Trojan on the performance of NoC. The results show packet drop has been reduced, and around 80 % of packets reached the destination address by mitigating the effect due to address Trojan. The throughput and latency of the NoC is increased by 70 %. Further Simulation results show that the proposed mitigation scheme is useful in limiting the malicious effect of hardware Trojans. Thus, an effort has been made to address the routing, architectural, and security challenges of NoC design. A three-tier solution is proposed to safeguard the data and resources of NoC from HT. The proposed Trojan cognizant routing algorithm (TCRA) limits the HTs to a single router. Another method to trick and find the HTs is data shuffling with Trojan detectability. The proposed method reduces the hazards the Trojan poses, such as data leakage, performance degradation, denial of service, and live locking of data packets,at the cost of a little extra delay and hardware.