Lightweight Block Cipher Optimizations for Resource Constrained Applications

Abstract

The work presented in the thesis is broadly in the domain of optimization of lightweight cipher architectures. The S-box optimization problem, the side-channel countermeasure problem for mitigating side-channel attacks, along with one resource-constrained application use case for the healthcare sector, form the focus of the work reported in the thesis. Resource-constrained applications are often involved in handling sensitive data and communicating with each other and end-users, necessitating security requirements. This calls for the encryption architectures to be lightweight. Further, optimising lightweight ciphers for hardware has been less explored, which opens the scope for research in this field. The motivation of choice for the selected research problem stems from the fact that the domain of lightweight cryptography is relatively less established. With increasing IoT devices becoming part and parcel of daily lives, trading off security and performance gains importance. The detailed analysis of different lightweight ciphers indicates that proposed architectures have better design and performance metrics with acceptable trade-offs. The proposed architectures are catered to meet resource-constrained application design and performance constraints. The implementation platforms, i.e. FPGA or ASIC, also influence the architecture’s resource utilization. In general, the speciality of the proposed optimized architectures is that they can apply to all the symmetric block ciphers, whether lightweight or conventional crypto algorithms. The thesis’s contribution begins with optimizing S-box architectures for lightweight ciphers. Initially, three S-box architectures have been proposed utilizing the logic synthesis approaches. The techniques include the reuse of minterms technique, which is a gate based approach, and the multiplexers-based implementation of the S-box architectures. The gate-based approach was observed to have utilized lesser area with a trade-off for delay. The MUX-based architectures have been more beneficial because they map efficiently with the FPGA resources, reducing the number of slices, without increasing the delay of the architectures. The next part of the thesis deals with the optimization of S-box architectures utilizing functional decomposition techniques. This includes six techniques utilizing the one and two variables decomposition, frequent variable elimination, Binary Decision Diagram, positive Davio expansion, and another hybrid method combining the latter and Shannon’s Decomposition methods. The architectures implemented based on these techniques include the multiplexers, gates, and/or a combination of both. The S-box architectures implemented using the techniques have been incorporated into the overall encryption architectures of PRESENT, Midori, KLEIN, GIFT, and RECTANGLE lightweight ciphers. The complete architectures have been evaluated on the FPGA platform with a 13.56 MHz frequency suitable for RFID applications and 2.45 GHz for ISM band applications. The S-box architectures are also evaluated for SAED90nm standard libraries to validate it for ASIC realization.The S-boxes implemented with the proposed techniques have resulted in optimized outcomes in terms of area, power and delay. The S-boxes have been included in the overall cipher architecture and proved to be better than the state-of-the art architectures. These results are tailor-made to meet the design specifications for IoT enabled devices, which have not been investigated earlier to the best of our knowledge. Apart from the S-box architecture optimizations, the thesis contributes to the datapath optimization of the substitution permutation network. In this regard, PRESENT and Midori lightweight cipher have been experimented with. The proposed architectures are so designed that the delay and power consumption of the designs have been significantly reduced compared to the 64-bit datapath. The low power metrics have been achieved by adding power-efficient selector modules, which reduce the dynamic power consumption of the overall architecture for both FPGA and ASIC platforms. The thesis also proposes the side-channel countermeasure using masking techniques with fewer overheads than existing techniques. The compact and high throughput architecture of Midori, designed earlier, inculcates a masking feature to make it resilient against side-channel power attacks. The proposed masking technique results in fewer overheads when compared with the existing masking methods. The last part of the thesis looks into the applicability of the proposed architectures to resource-constrained applications in a healthcare setup. The encryption and decryption processes of the Fitbit dataset have been illustrated. An encryption decryption model is illustrated using the proposed S-box architectures with associated trade-offs.