Post-Manufacturing Performance Sensing and Healing Techniques in Analog and Radio Frequency Integrated Circuits

Abstract

Analog and radio frequency integrated circuits (RFICs) are increasingly susceptible to process variations, leading to significant performance degradation and low fabrication yields. The conventional strategy of over-designing circuits to address this issue imposes significant area and power overheads, making it unsuitable for high-speed and portable applications. An alternative approach is to sense and heal the chip performance impairment using suitable tuning control in the post-manufacturing stage for yield improvement. Test time reduction in post-manufacturing performance sensing and healing of analog and RFICs is a challenging task that urges the development of advanced sensing techniques integrated with an efficient healing algorithm. This work focuses on the different post-manufacturing sensing and healing techniques for analog circuits with the objective of reducing test time and test cost. A Machine Learning (ML) based indirect sensing and one-step healing framework have been used in this work. Non-intrusive process variation sensors (PVSs) are used for performance sensing. PVSs are designed in a systematic manner through the identification of vital process parameters affecting the performance and accordingly, the Test Signatures (T Ss) that best reflect the performance are extracted. A current starved voltage controlled oscillator (CSVCO), which is a key element in a phase locked loop (PLL) is considered the test circuit to validate the proposed sensing and healing framework. Indirect performance sensing and healing using ML needs a large dataset to facilitate better model training. To reduce the lengthy simulation time in extracting the data for effective model training, a Generative Adversarial Network (GAN) is used to generate synthetic data during the design phase. The proposed approach accelerates the design cycle and reduces the design costs for building an effective ML model for performance prediction. Finally, an on-chip approach for autonomous sensing and healing of long-term jitter in PLL is proposed. A compact and energy efficient Built-in–Jitter Sensor (BIJS) is proposed to sense the Long-Term Jitter (tLT J ) in a PLL. Also, a digital self-healing circuit is proposed to heal the tLT J of a process-impaired PLL to an acceptable limit.