Varghese, George Tom (2009) Phase Locked Loop Design as a Frequency Multiplier. MTech thesis.
High-performance digital systems use clocks to sequence operations and synchronize between functional units and between ICs. Clock frequencies and data rates have been increasing with each generation of processing technology and processor architecture. Phase locked-loops (PLLs) are widely used to generate well-timed on-chip clocks in high-performance digital systems. A PLL is a closed loop frequency system that locks the phase of an output signal to an input reference signal. PLL’s are widely used in computer, radio, and telecommunications systems where it is necessary to stabilize a generated signal or to detect signals. The term “lock” refers to a constant or zero phase difference between two signals. The signal from the feedback path is compared to the input reference signal, until the two signals are locked. If the phase is unmatched, this is called the unlocked state, and the signal is sent to each component in the loop to correct the phase difference. These components consist of the Phase Frequency Detector (PFD), the charge pump (CP), the low pass filter (LPF), the voltage controlled oscillator (VCO) and divide by counter. The PFD detects any phase differences in and and then generates an error signal. According to that error signal the CP either increases or decreases the amount of charge to the LPF. This amount of charge either speeds up or slows down the VCO. The loop continues in this process until the phase difference between and is zero or constant—this is the locked mode. After the loop has attained a locked status, the loop still continues in the process but the output of each component is constant. The output signal has the same phase and/or frequency as .A divider can be used in the feedback path to synthesize a frequency different than that of the reference signal. The application I chose in designing the PLL was a frequency synthesizer. A frequency synthesizer generates a frequency that can have a different frequency from the original reference signal.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Phase Locked Loop, Phase Frequency Detector, Voltage Controlled Oscillator|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||George Tom Varghese|
|Deposited On:||25 May 2009 12:31|
|Last Modified:||25 May 2009 12:31|
|Supervisor(s):||Mahapatra, K K|
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