Design and Analysis of Novel Charge Pump Architecture for Phase Locked Loop

Abstract

Modern wireless communication systems employ Phase Locked Loop (PLL) mostly for synchronization, clock synthesis, skew and jitter reduction. The performance of PLL affects significantly the signal recovery and system functionality in these systems. Charge pump being one of the important components, decides the functional parameters of PLL. This thesis simulates and analyses some of the major reported charge pump architectures. The present work also proposes an efficient architecture of CMOS charge pump and analyses the design considerations for the proposed circuit. The novel charge pump is designed in Cadence Virtuoso environment and implemented using GPDK090 library of 0.1µm technology and a supply voltage of 1.8V. The performance parameters are compared with other standard and latest charge pump based architectures of PLL. The PLL implemented using proposed charge pump is found to exhibit very low acquisition time of 850ns and consume substantially low power of 0.6041mW.