Implementation of PCS of Physical Layer for PCI Express

Abstract

PCI Express is third generation Computer Bus to inter connect peripherals in a Computer, Servers, Mobile sets and systems. PCS is the sublayer of the physical layer of PCI Express 1.0. The major constituents of this layer are transmitter and receiver. Transmitter comprises of 8b/10b encoder. The Primary purpose of this scheme is to embed a
clock into the serial bit stream of transmitter lanes. No clock is transmitted along with the serial
data bit stream. This eliminates EMI noise and provides DC balance. Receiver comprises of special symbol detector, elastic buffer and 8b/10b decoder. Elastic buffer
is nothing but a FIFO operated with two clocks. While a transaction, at one device Recovered Clock from the received data and the clock transmitted at another device may slightly differ. So, Recovered clock and the receiver clock will differ. In this case data corruption will occur. To
avoid this situation elastic buffers are used and the data recovered through special symbols. When ever recovered clock is faster than system clock, there is overflow in the buffer. And when recovered clock is slower than system clock underflow in the elastic buffer will occur. 8b/10b decoder gives 8bit character and data/control signals. Disparity error and Decode error can be known though this module. If any error is present in the received data then loopback
signal is generated. This work uses VHDL to model different blocks of the PCS of physical layer of PCI Express.
The RTL code is simulated, synthesized and implemented using the ISE 10.1 from Xilinx and the Spartan 3E FPGA was targeted for implementation.