Design and Verification of WISHBONE Bus Interface for SOC Integration

Swain, A K (2010) Design and Verification of WISHBONE Bus Interface for SOC Integration. MTech by Research thesis.



The rapid development in the field of mobile communication, digital signal processing (DSP) motivated the design engineer to integrate complex systems of multimillion transistors in a single chip. The integration of the transistor in a single chip greatly increases the performance of the system while reduction in system size.
Recently, there is a considerable increase in the application front in several areas of engineering and technology. Moore’s law states that integration density gets doubled every two years, so the complexity of the integrated circuits also increases by keeping the used chip area constant. In order to keep pace with the levels of integration available, design engineers have developed new methodologies and techniques to manage the increased complexity in these large chips.
System-on-Chip (SOC) design is proposed as an extended methodology to this problem where pre-designed and pre-verified IP cores of embedded processors,
memory blocks, interface blocks, and analog blocks are combined on a single chip targeting a specific application. These chips may have one or more processors on chip, a large amount of memory, bus-base architectures, peripherals, co processors, and I/O channels. These chips integrates systems far more similar to the boards
designed ten years ago that to the chips of even a few years ago. The primary drivers for this are the reduction of power, smaller form factor, and lower overall cost. SOC
offers many benefits such as smaller space requirements with higher performance.

Item Type:Thesis (MTech by Research)
Uncontrolled Keywords:System On Chip, WISHBONE Bus,Open Core
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:1567
Deposited By:Ayas Swain
Deposited On:10 May 2010 15:08
Last Modified:11 May 2010 06:58
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Supervisor(s):Mahapatra, K K

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