OVM compliant verification for a wishbone compatible i2c master controller core

Mohanty, Abinash and Xess, Manoranjan and Mahapatra, Madhurita (2010) OVM compliant verification for a wishbone compatible i2c master controller core. BTech thesis.



Increasing design complexity and concurrency of Integrated Circuits has made traditional directed testbenches an unworkable solution for testing. Today, testing as a word has been substituted with verification. Verification engineers have to ensure what goes to the factory for manufacturing is an accurate representation of the design specification. Inter Integrated Circuit (I2C) bus is a very widely used communication protocol in embedded system design due to its hardware simplicity and high data transfer rates capability. Most ICs incorporate I2C interface. Thus the ASIC design process of these ICs calls for robust, independent and exhaustive verification to reduce the risks of their failures. Open Verification Methodology (OVM) is an open source verification methodology library intended to run on multiple platforms and be supported by multiple EDA vendors. This thesis attempts to study and hence introduces a comprehensive verification environment for the latest specifications of the I2C bus protocol realized in the OVM platform, a new industry standard for comprehensive verification due to its rich base classes and OOP features. This work has been challenging since very few work has been reported in this domain for reference.

Item Type:Thesis (BTech)
Uncontrolled Keywords:OVM, I2C bus protocol, code coverage, functional coverage, OOP
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:1908
Deposited By:Mr. Abinash Mohanty
Deposited On:17 May 2010 16:48
Last Modified:13 Jun 2012 17:20
Supervisor(s):Acharya, D P

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