A Novel High Speed Cmos Comparator With Low Power Disipation And Low Offset

Parida, Debasis (2010) A Novel High Speed Cmos Comparator With Low Power Disipation And Low Offset. MTech thesis.



A Novel High Speed CMOS Comparator with low power dissipation, low offset, low noise and high speed is proposed. Inputs are reconfigured from typical differential pair comparator such that near equal current distribution in the input transistors can be achieved for a meta-stable point of the comparator. Restricted signal swing clock for the tail current is also used to ensure constant currents in the differential pairs. Nearly 18 mv offset voltage is easily achieved with the proposed structure making it favourable for flash and pipeline data conversion applications.
The proposed topology is based on hysteresis using positive feedback, has a small power dissipation, less area, and it is shown to be very robust against transistor mismatch, noise immunity. Test structures of the comparators, designed in GPDK 90 nm are measured to determine offset –voltage, power - dissipation and speed. These are compared and the superior features of the proposed comparator are established.

Item Type:Thesis (MTech)
Uncontrolled Keywords:CMOS, COMPARATOR, CADENCE, GPDK 90nm
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:1980
Deposited By:Design of an Application Specific Instuction set Processor using LISA Umakanta Nanda
Deposited On:29 May 2010 09:04
Last Modified:29 May 2010 09:04
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Supervisor(s):Mahapatra, K K

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