Ram, Ashish Kumar and Sahoo, Sandip (2011) Intelligent optimization of Circuit placement on FPGA. BTech thesis.
Field programmable gate arrays (FPGAs) have revolutionized the way digital systems are designed and built over the past decade. With architectures capable of holding tens of millions of logic gates on the horizon and planned integration of configurable logic into system-on-chip platforms, the versatility of programmable devices expected to increase dramatically. Placement is one of the vital steps in mapping a design into FPGA in order to take best advantage of the resources and flexibility provided by it. Here, we propose to test techniques of Placement Optimization on MCNC Benchmark circuits. PSO (Particle Swarm Optimization) has been implemented on circuit netlist with bounding box as cost function. Alternate cost functions were also employed to verify efficiency of optimization. Furthermore, lazy descent was introduced into the algorithm to impede premature convergence. Different values of acceleration and weighing factors were used in the implementation and corresponding convergence results were analyzed.
Keywords- FPGA Placement; Particle Swarm Optimization; MCNC Benchmarks Circuits; Bounding Box driven Placement.
|Item Type:||Thesis (BTech)|
|Uncontrolled Keywords:||FPGA Placement; Particle Swarm Optimization; MCNC Benchmarks Circuits; Bounding Box driven Placement.|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > Soft Computing|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Mr. Ashish Kumar Ram|
|Deposited On:||17 May 2011 14:56|
|Last Modified:||13 Jun 2012 17:21|
|Supervisor(s):||Acharya, D P|
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