FPGA Implementation of digital controller for shunt active power filter to reduce harmonics and reactive power

Ram, Saswat Kumar (2011) FPGA Implementation of digital controller for shunt active power filter to reduce harmonics and reactive power. MTech thesis.



Most of the pollution issues created in power systems are due to the non-linear characteristics and fast switching of power electronic equipment. Power quality issues are becoming stronger because sensitive equipment will be more sensitive for market competition reasons, equipment will continue polluting the system more and more due to cost increase caused by the built-in compensation and sometimes for the lack of enforced regulations. Efficiency and cost are considered today almost at the same level. Active power filters have been developed over the years to solve these problems to improve power quality. Among which shunt active power filter is used to eliminate and load current harmonics and reactive power compensation. The active power filter (APF) is implemented with PWM based current controlled voltage source inverter (VSI). This VSI switching signals are generated through proposed three-level hysteresis current controller (HCC) that achieves significant reduction in the magnitude and variation of the switching frequency; it is indicating improved performance compared to 2-level HCC. The shunt APLC system is modeled and investigated under different unbalanced non-linear load conditions using MATLAB programs. The simulation results reveal that the active power filter is effectively compensating the current harmonics and reactive power at point of common coupling. The active power line conditioner system is in compliance with IEEE 519 and IEC 61000-3 recommended harmonic standards. Due to non-linear characteristics the load current gets distorted which causes undesirable effects like heating, equipment damages, EMI effects etc. in power network. The active power filter (APF) is the best solution for eliminating the harmonics caused by the non-linear loads. This work presents the three-phase four-wire active filter for power line conditioning (PLC) to improve power quality in the distribution network and implementation of a digitally controlled APF. Designed in Hardware Description Language (VHDL or VERILOG), the controller becomes independent of process technology. Synchronous reference frame is used for generation of reference current. PI currents algorithm and hysteresis current controller (HCC) together is written in VHDL code and is implemented using FPGA platform. Various simulation results are presented under steady state and transient state condition and performance is analyzed. Simulation results obtained shows that the performance of three phase system with APF is found to be better and digital controller add a new aspect for the controller from low cost, high speed and hardware implementation point.PWM and hysteresis based current control is used to obtain the switching signals to the voltage source inverter(VSI).

Item Type:Thesis (MTech)
Uncontrolled Keywords:APF,Harmonics,Power
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:2714
Deposited By:Ram Saswat Kumar
Deposited On:01 Jun 2011 14:14
Last Modified:01 Jun 2011 14:14
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Supervisor(s):Mahapatra, K K

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