VHDL implementation of reed-solomon coding

Abstract

Forward Error Correction technique depending on the properties of the system or on the application in which the error correcting is to be introduced. Error control coding techniques are based on the addition of redundancy to the information message according to a prescribed rule thereby providing data a higher bit rate. This redundancy is exploited by decoder at the receiver end to decide which message bit actually transmitted. Reed-Solomon codes are an important sub – class of non binary Bose-Chaudhuri-Hocquenghem (BCH) codes.
In digital communication, Reed-Solomon (RS) codes refer to as a part of channel coding that had becoming very significant to better withstand the effects of various channel impairments such as noise, interference and fading. This signal processing technique is designed to improve communication performance and can be deliberate as medium for accomplishing desirable system trade-offs.
Galois field arithmetic is used for encoding and decoding of Reed – Solomon codes. Galois field multipliers are used for encoding the information block. The encoder attaches parity symbols to the data using a predetermined algorithm before transmission. At the decoder, the syndrome of the received codeword is calculated. VHDL implementation creates a flexible, fast method and high degree of parallelism for implementing the Reed – Solomon codes.
The purpose of this thesis is to evaluate the performance of RS coding system using M-ary modulation over Additive White Gaussian Noise AWGN channel and implementation of RS encoder in VHDL. Computer simulation tool and MATLAB will be used to create and run extensively the entire simulation model for performance evaluation and VHDL is used to implemented the design of RS encoder.
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