Design and Analysis of an Efficient Phase Locked Loop for Fast Phase and Frequency Acquisition

Abstract

The most versatile application of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor, networking, communication systems, and frequency synthesizers. Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks in high-performance digital systems. Modern wireless communication systems employ Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter reduction. Because of the increase in the speed of the circuit operation, there is a need of a PLL circuit with faster locking ability. Many present communication systems operate in the GHz frequency range. Hence there is a necessity of a PLL which must operate in the GHz range with less lock time. PLL is a mixed signal circuit as its architecture involves both digital and analog signal processing units. The present work focuses on the redesign of a PLL system using the 90 nm process technology (GPDK090 library) in CADENCE Virtuoso Analog Design Environment. Here a current starved ring oscillator has been considered for its superior performance in form of its low chip area, low power consumption and wide tuneable frequency range. The layout structure of the PLL is drawn in CADENCE VirtuosoXL Layout editor. Different types of simulations are carried out in the Spectre simulator. The pre and post layout simulation results of PLL are reported in this work. It is found that the designed PLL consumes 11.68mW power from a 1.8V D.C. supply and have a lock time 280.6 ns. As the voltage controlled oscillator (VCO) is the heart of the PLL, so the optimization of the VCO circuit is also carried out using the convex optimization technique. The results of the VCO designed using the convex optimization method is compared with traditional method.