A verilog-based simulation methodology for estimating power and area

Abstract

Accurate modeling and estimating of the power dissipation in the early stages of the design flow is becoming more important, as the aggressive scaling of transistors results in higher leakage currents. New and complex systems are being implemented using highly advanced Electronic Design Automation (EDA) tools. As the complexity increases, the dissipation of power has emerged as one of the very significant design constraints. Low power designs are not only used in small size applications like cell phones and handheld devices but also in high-performance computing applications. Numerous tools have emerged in recent years to address this issue of power consumption and power optimization. With a vast number of these power measurement tools emerging, analyzing power consumed by digital circuits has not only become easier but also more effective methods are deployed to optimize digital circuits to dissipate less power.
In this work, we present a Verilog-based technique to estimate an accurate power dissipation of a design considering the state-dependency of the leakage power and path dependency of dynamic power. We develop the verilog models of cells which trace the probability of the static levels of the signals in the course of a simulation. Then, these data are used to calculate the power dissipation in the overall design. The power dissipation of some benchmark circuits is estimated using the proposed approach.