Design and Modeling of I2C Bus Controller

Abstract

This thesis is concerned with the design of I2C bus controller and the interface between the I2C devices i.e. microcontroller (AT89C51) and EEPROM (AT24C16). The I2C is a two wire serial protocol. Hence I2C components can be interfaced by using only two lines. First one is serial data (SDA) line and second is serial clock (SCL) line. The design architecture consists of a master controller and a slave. The master generates the START condition when SCL is
HIGH and SDA is having a transition from HIGH to LOW. Master also generates STOP condition when SCL is in HIGH and SDA is having a transition from LOW to HIGH. Beside
these two functions master also transfers and receives data to/from different slave devices. When master transmits data to slave receiver then it is known as WRITE mode of operation and when master receives data from slave transmitter then it is known as READ mode of operation. The microcontroller and EEPROM are interfaced through I2C bus. Data send, read and write particularly these operations are carried out and the behavior of I2C protocol is examined. In later section the I2C master controller is designed in verilg HDL. By describing the design in HDL, functional verification of the design can be done early in the design cycle.Since designers work at the high level language, they can optimize and modify the design module until it meets the desired functionality. The test bench program has to be developed to test the design module. The test bench gives the input to the design module & verifies the outputs. The test bench has to be written in such way to check the design module in all possible conditions.