Jana, Prateek Kumar (2011) Design of 8B/10B encoder and its OVM compliant verification IP. MTech thesis.
Today in the era of modern technology micro electronics play a very vital role in every aspects of life of an individual, increasing use for micro electronics equipments increases the demand for manufacturing its components and its availability, reducing its manufacturing time, resulting in increasing the failure rate of the finished product. In order to overcome this problem the Technocrats develop a method called Verification, a process which is a part of manufacturing microelectronics products and its main objective is to verify the intent of the design is preserved in its implementation.
The work embodied in the thesis presents the design of 8B/10B encoder IP and its Verification using OVM. Coverage analysis is a vital part of the verification process; it gives idea that to what degree the source code of the DUT has been tested. The Code coverage analysis increases the verification efficiency enabling the verification engineer to isolate the areas of un-tested code. It has become a criterion for finishing unit level testing as it needs to verify every feature of component or unit.
In the later section of the thesis, The Open Verification Methodology (OVM) is used to design a VIP and verify the encoder IP; the verification IP is built by developing verification components using SystemVerilog and OVM class library, which provides the suitable building blocks to design the test environment.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||VLSI,Verification,Open Verification Methodology,VIP|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Mr. Prateek Kumar Jana|
|Deposited On:||07 Jun 2011 16:53|
|Last Modified:||07 Jun 2011 16:53|
|Supervisor(s):||Acharya, D P|
Repository Staff Only: item control page