High Performance Logic for Arithmetic Circuits

Das, Neeharika (2012) High Performance Logic for Arithmetic Circuits. BTech thesis.

[img]PDF (B tech thesis)


The objective of this project is to design high performance arithmetic circuits which are faster and have lower power consumption using a new dynamic logic family of CMOS and to analyze its performance for sequential circuits and effects upon cascading. This new dynamic logic family is known as Feedthrough logic. It has two basic structures: high speed (HS0) and low power (LP0). It allows for commencement of evaluation in a computational block before its evaluation phase begins, and quickly performs a final evaluation as soon as the inputs are valid. This dynamic logic family is best suited to arithmetic circuits because the critical path is made of a long chain of cascaded inverting gates. As the major advantage of this logic which is higher speed is observed upon cascading, it’s most suitable for arithmetic circuits. We compare a set of ripple carry adders 4 bit and 16 bit in domino logic with the two basic structures derived. Experimental results have shown that the lower power structure provides for smaller power delay product when compared with domino logic.

Certain modifications in the logic style are proposed to optimize the performance when applied to a single ended or double ended flip flops. The effects upon cascading are analyzed by using a 4-bit register. As delay is not propagated in a register circuit or any other synchronous sequential circuit (the circuit being edge triggered), the major advantage of this logic which is observed upon cascading cannot possibly be observed for sequential circuits. So even though the circuit can be optimised by feedthrough logic, this logic is not preferred for sequential circuits.

So finally we have carried out the tapeout of 16 bit adder in LP0 using 180 UMC CMOS process flow.

Item Type:Thesis (BTech)
Uncontrolled Keywords:Dynamic logic, CMOS logic circuits, Feedthrough logic, High speed arithmetic circuits, Low power arithmetic circuits, latches, single ended edge triggered master slave flip flop, double ended pulse triggered flip flop, register based sequential circuits.
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:3608
Deposited By:Das Neeharika
Deposited On:29 May 2012 15:14
Last Modified:29 May 2012 15:14
Supervisor(s):Mahapatra, K K

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