Developing an efficient IEEE754 compliant FPU in verilog

Devadasi, Ruby (2012) Developing an efficient IEEE754 compliant FPU in verilog. BTech thesis.



A floating-point unit (FPU) colloquially is a math coprocessor, which is a part of a computer system specially designed to carry out operations on floating point numbers [1]. Typical operations that are handled by FPU are addition, subtraction, multiplication and division. The aim was to build an efficient FPU that performs basic as well as transcendental functions with reduced complexity of the logic used reduced or at least comparable time bounds as those of x87 family at similar clock speed and reduced the memory requirement as far as possible. The functions performed are handling of Floating Point data, converting data to IEEE754 format, perform any one of the following arithmetic operations like addition, subtraction, multiplication, division and shift operation and transcendental operations like square Root, sine of an angle and cosine of an angle. All the above algorithms have been clocked and evaluated under Spartan 3E Synthesis environment. All the functions are built by possible efficient algorithms with several changes incorporated at our end as far as the scope permitted. Consequently all of the unit functions are unique in certain aspects and given the right environment(in terms of higher memory or say clock speed or data width better than the FPGA Spartan 3E Synthesizing environment) these functions will tend to show comparable efficiency and speed ,and if pipelined then higher throughput.

Item Type:Thesis (BTech)
Uncontrolled Keywords:Floating Point Unit,Floating Point operation,efficiency
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Computer Science
ID Code:3610
Deposited By:MS. LIPSA SAHU
Deposited On:29 May 2012 15:22
Last Modified:14 Jun 2012 10:03
Supervisor(s):Khilar, P M

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