Hardware Implementation of Densely Packed Decimal Encoding-An optimized approach supporting run-time user input

Abstract

BCD Encoding scheme represents each Decimal digit(Base 10) by its own binary sequence of 4 bits.Though this scheme remains highly use- ful for storage and simple operations on decimal data,compact represen- tations hold more signicance in some applications.An encoding scheme
was proposed by Chen and Ho named "Chen-Ho Encoding".This encoding represents a three digit decimal in 10 bits unlike BCD which requires 12 bits,thus giving more eciency and less wastage.This uses an algorithm which uses simple boolean operations to compress the 12 BCD bits into
10 and also reverse the process[1].DPD encoding is an improvisation of Chen-Ho encoding scheme.This
overcomes the limitation of Chen-Ho encoding which requires the decimal number to be a multiple of 3 digits[2].This codes arbitrary length deci- mal numbers as 10 bits.This enables the best use of available resources like storage space and hardware registers.BCD encoding results in high
wastage of bit-pattern space.The objective of DPD compression is to use this space for a long string of digits.This thesis embodies the work done to implement an optimized Densely Packed Decimal (DPD) encoding on hardware using VHDL and Xilinx Spartan 3E FPGA.