FPGA implementation of adaptive filter architectures

Abstract

This thesis proposes an FPGA Implementation of an Adaptive Filter architecture using LMS algorithm. Adaptive filters are commonly used in a wide range of applications such as Echo cancellation, Noise cancellation, Prediction, Adaptive interference canceling, System modeling or system identification, Radar signal processing, Equalizations of communication channels, Biomedical signal enhancements, Navigational systems, Digital communication Receiver, Adaptive antenna systems beamforming and many more. In this thesis, adaptive filter architecture implemented mainly application for noise cancellation, system identification and channel equalization. For noise cancellation, architecture is taken both sequential as well as parallel. For implementing Adaptive filter architecture, LMS algorithm is used because of low computational complexity, simplicity and its better performance in different running environments. In this thesis most of the adaptive filter architecture is taken a Gaussian noise, but in many practical real situation it is seen that, using Gaussian noise is not sufficient, because Gaussian noise has a fixed shape “Bell curve “ but many situation can’t predict the noise shape, So impulsive noise consideration is very important. Impulsive noise generally has no fixed shape it varying large amplitude spikes which is overlapped so many samples. So it is very difficult to detect or cancel it. The impulsive noise is generally destructive types of signal distortion. So in this thesis impulsive noise reduction is also main aim of implementation. In all adaptive filter architecture try to minimize error i.e. minimization of different between the desired output and the real one for all the input vectors.Nowadays, the use of Field programmable gate arrays (FPGAs) is growing. Field programmable gate arrays (FPGAs) are widely used in many areas such as audio and video, Digital signal processing, Image signal Processing, Digital communication systems, mobile communication system and many other embedded applications, because of their high performance, parallel processing ability and flexibility. Implementation of FPGA, generally two ways either writing a HDL Code or by using a System Generator tool. Using Hardware Description Languages (HDL) for FPGA implementation is too time consuming and needs background in a chip design, so in thesis all architecture implemented on FPGA using Xilinx Spartan-3E Starter Kit as the target board and Xilinx System Generator (XSG). Using System Generator tool is easy because it is generates automatically HDL (VHDL/Verilog) code. Generated HDL code can be synthesized and implemented in the Xilinx FPGAs.