Analysis and application of improved feedthrough logic

Sahoo, Sauvagya Ranjan (2012) Analysis and application of improved feedthrough logic. MTech thesis.



Continuous technology scaling and increased frequency of operation of VLSI circuits leads to increase in power density which raises thermal management problem. Therefore design of low power VLSI circuit technique is a challenging task without sacrificing its performance. This thesis presents the design of a low power dynamic circuit using a new CMOS domino logic family called feedthrough (FTL) logic. Dynamic logic circuits are more significant because of its faster speed and lesser transistor requirement as compared to static CMOS logic circuits. The need for faster circuits compels designers to use FTL as compared static and domino CMOS logic and the requirement of output inverter for cascading of various logic blocks in domino logic are eliminated in the proposed design. The proposed circuit for low power (LP-FTL) improves dynamic power consumption as compared to the existing FTL and to further improve its speed we propose another circuit (HS-FTL). This logic family improves speed at the cost of dynamic power consumption and area. Proposed modified FTL circuit families provide better PDP as compared to the existing FTL. Simulation results of both the proposed circuit using 0.18 µm, 1.8 V CMOS process technology indicate that the LP-FTL structure reduces the dynamic power approximately by 42% and the HS-FTL structure achieves a speed up- 1.4 for 10-stage of inverters and 8-bit ripple carry adder in comparison to existing FTL logic. Furthermore, we present various circuit design techniques to improve noise tolerance of the proposed FTL logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (average noise threshold energy) metric is used for the analysis of noise tolerance of proposed FTL. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at 0.18-µm, 1.8 V CMOS process technology show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power.
Continuous scaling of technology towards the nanometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity.

Item Type:Thesis (MTech)
Uncontrolled Keywords:Feedthrough logic,Ripple carry adder, Noise immunity
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:3975
Deposited By:Unnamed user with email
Deposited On:12 Jun 2012 11:43
Last Modified:14 Jun 2012 15:02
Supervisor(s):Mahapatra, K K

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