Controller area network protocol; design to tape out

Jena, Tapas Ranjan (2012) Controller area network protocol; design to tape out. MTech thesis.



Control area network (CAN) is a two- wired, half duplex, high-speed network system, that is far superior to conventional serial communication protocol such as RS232, with regards to functionality and reliability and yet CAN implementations are more cost effective. CAN is a serial network technology that is widely used in real-time automobile control. It is a multi-master serial bus that uses broadcast to transmit to all CAN nodes. It is good for short message transfer. Its data transfer size is limited to 8 bytes with 1 Mbps speed. It provides a significant reduction in wiring complexity and additionally makes it easy to connect with several devices using a single bus. CAN provides an effective mechanism for clock synchronization known as “bit-stuffing”. It is very difficult to predict the precise transmission time of message which leads to an adverse impact on many time critical applications. To mitigate above problem different “bit-stuffing” techniques such as XOR masking and Software Bit Stuffing (SBS) are available in the literature. In this thesis a novel alternative method known as Eight-to-Eleven Modulation (EEM) technique is used for “bit-stuffing” and a comparison is brought with existing SBS technique and the superior features of EEM is derived. The proposed technique is validated through FPGA implementation.In this thesis, design to tape out is perform for a CAN controller. The Register Transfer Level (RTL) coding is done by Verilog HDL (Hardware Description Language). Synopsys VCS simulator is used to simulate the RTL code. Synthesized netlist is created by using Synopsys Design Vision. Cadence SoC encounter is used for automatic place and route and cadence icfb is used for final integration of the design with the pad ring. Final GDS II file is created for tape-out. UMC 180 mixed mode library is used for implementing the system with six metal layers and one poly layer.

Item Type:Thesis (MTech)
Uncontrolled Keywords:RTL, GDS, Simulation, Test bench, Verilog, CAN, Tape out, Synthesis, I/O PAD, EEM, SBS, Bit stuffing
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:4057
Deposited By:Unnamed user with email
Deposited On:13 Jun 2012 09:26
Last Modified:13 Jun 2012 09:26
Supervisor(s):Swain, A K and Mahapatra, K K

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