Samal, Lopamudra (2012) Application specific instruction set processor design for embedded application using the coware tool. MTech thesis.
An Application Specific Instruction Set Processor (ASIP) is widely used as a System on a Chip(SoC) Component. ASIPs possess an instruction set which is tai-lored to benefit a specific application. Such specialization allows ASIPs to serve as an intermediate between two dominant processor design styles- ASICs which has high processing abilities at the cost of limited programmability and Programmable solu-tions such as FPGAs that provide programming exibility at the cost of less energy eficiency. In this dissertation the goal is to design ASIP, keeping in mind a temper-ature sensor system. The platform used for processor design is LISA 2.0 description language and processor designing environment from CoWare. Coware processor de-signer allows processor architecture to be defined at an abstract level and automatic generation of chain of software tools like assembler, linker and simulator for functional verification followed by RTL level description. RTL level description is used to gen-erate synthesized report of the design using RTL compiler and finally the layout is created using Cadence encounter.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||32-bit embedded processor, Language for instruction set architecture(LISA), Coware, Register transfer level(RTL), XILINX, Cadence RTL compiler, Cadence encounter,|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > Sensor Networks|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Unnamed user with email email@example.com|
|Deposited On:||13 Jun 2012 09:45|
|Last Modified:||13 Jun 2012 09:45|
|Supervisor(s):||Mahapatra, K K and Swain, A K|
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