Tiriveedhi, Madhu Babu (2008) *Low latency digit-recurrence reciprocal and square-root reciprocal algorithm and architecture.* MTech thesis.

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## Abstract

The reciprocal and square root reciprocal operations are important in several applications such as computer graphics and scientific computation. For the two operations, an algorithm that combines a digit-by-digit module and one iteration of the Newton-Raphson approximation is used. The latter is implemented by a digit-recurrence, which uses the digits produced by the digit-by-digit part. In this way, both parts execute in an overlapped manner, so that the total number of cycles is about half of the number that would be required by the digit-by-digit part alone. Since the approximation does not produce correct rounding in a few cases, for applications where exact rounding is required, the result is only computed by the digit-by-digit module. Radix-4 implementations for combined unit are described. The result of the evaluation shows that the cycle time is the same as that of the digit-by-digit unit and that, as a consequence, the execution time is almost halved. Because of the approximation part, the area almost doubles of the digit-by-digit area. In this Dissertation, an implementation algorithm and architecture for low latency digit recurrence reciprocal and squareroot reciprocal has been presented. The implementation is based on Radix-4, considering execution time and system complexity. This project aims to provide modules written in the Very High Speed Integrated Circuit Hardware Description Language (VHDL) that can be used to model low latency digit recurrence reciprocal and square root reciprocal architecture.

Item Type: | Thesis (MTech) |
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Uncontrolled Keywords: | VLSI design and embedded System |

Subjects: | Engineering and Technology > Electronics and Communication Engineering > VLSI |

Divisions: | Engineering and Technology > Department of Electronics and Communication Engineering |

ID Code: | 4181 |

Deposited By: | Hemanta Biswal |

Deposited On: | 20 Jun 2012 14:21 |

Last Modified: | 20 Jun 2012 14:21 |

Supervisor(s): | Rath, G S |

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