VHDL implementation of 32 bit interlock collapsing ALU

Acharya, Himanshu Shekhar and Neeraj, Nem Kumar and Sahoo, Bibhuti Prasad (2007) VHDL implementation of 32 bit interlock collapsing ALU. BTech thesis.



An important area in computer architecture is parallel processing. Machines employing parallel processing are called parallel machines. A parallel machine executes multiple instructions in one cycle. However, parallel machines have a limitation, they cannot execute interlocked instructions. They are executed in serial like any serial machine. It takes more than one cycle to execute multiple instructions causing performance degradation. In addition there is hardware underutilization as a result of serial execution in parallel machine. The solution requires a special kind of device called “Interlock collapsing ALU”. The Interlock Collapsing ALU, unlike conventional 2-1 ALU’s is a 3-1 ALU. The proposed device executes the interlocked instructions in a single instruction cycle, unlike other parallel machines, resulting in high performance. The resulting implementation demonstrates that the proposed 3-1 Interlock Collapsing ALU can be designed to outperform existing schemes for ICALU, by a factor of at least two. The ICALU is implemented in VHDL. Its functionality is verified through simulation.

Item Type:Thesis (BTech)
Uncontrolled Keywords:ALU, VHDL
Subjects:Engineering and Technology > Electrical Engineering
Divisions: Engineering and Technology > Department of Electrical Engineering
ID Code:4226
Deposited By:Hemanta Biswal
Deposited On:26 Jun 2012 16:32
Last Modified:26 Jun 2012 16:32
Supervisor(s):Das, S

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