FPGA implementation of an hearing aid algorithm using booth wallace multiplier

Abstract

Approximately 10% of the world’s population suffers from some type of hearing loss, yet only small percentage of this statistic use the hearing aid. The stigma associated with wearing a hearing aid, customer dissatisfaction with hearing aid performance, the cost and the battery life. Through the use of digital signal processing the digital hearing aid now offers what the analog hearing aid cannot offer. It proposes the possibility of flexible gain processing, updating filter coefficients using adaptive techniques and digital feed back reduction, etc. Currently lot of attention is being given to low power VLSI design. Major focus in this thesis is given to the impact of multipliers on the power consumption of digital hearing aids. At first booth multiplier and booth Wallace multipliers are designed. The multiplier which consumes less power is taken for designing hearing aid component. The implementation of the Hearing Aid system includes spectral sharpening for speech enhancement and spectral sharpening for noise reduction. A fundamental building block, an adaptive filter, analysis filter, synthesis filter are implemented using Booth multiplier and Booth Wallace multiplier. The simulation of the hearing aid is done both in MATLAB and VHDL. The results from MATLAB and VHDL are compared. The hearing aid is constructed, targeting FPGA. Using the synthesis report and the power calculation report we compare the relative power consumption of the adaptive decorrelator; analysis filter and synthesis filter for these multipliers. The results show that the power consumption is reduced using Booth Wallace multiplier and also that using this multiplier speed is increased. How ever, since the total power consumption is dominated by the FIR, IIR lattice filters, and the total power saving depends on the order of the filter. The hearing aid component is designed in VHDL and implemented in FPGA(VIRTEXII PRO) kit.