Pandu , Sagara (2007) Design and VLSI implementation of a decimation filter for hearing Aid applications. MTech thesis.
Approximately 10% of the world’s population suffers from some type of hearing loss, yet only small percentage of this statistic use the hearing aid. The stigma associated with wearing a hearing aid, customer dissatisfaction with hearing aid performance, the cost and the battery life. Through the use of digital signal processing the digital hearing aid now offers what the analog hearing aid cannot offer. Currently lot of attention is being given to low power VLSI design. More and more people around the world suffer from hearing losses. The increasing average age and the growing population are the main reasons for this. The decimation filter used for hearing aid applications is designed and implemented both in MATLAB and VHDL. The decimation filter is designed using the distributed arithmetic multiplier in VHDL. Each digital filter structure is simulated using Matlab and its complete architecture is captured using Simulink. The resulting architecture is hardware efficient and consumes less power compared to conventional decimation filters. Compared to the comb-FIR-FIR architecture, the designed decimation filter architecture using Comb-half band FIR-FIR contributes to a hardware saving and reduces the power dissipation.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||VLSI, MATLAB, VHDL, FIR-FIR|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Hemanta Biswal|
|Deposited On:||13 Jul 2012 15:29|
|Last Modified:||13 Jul 2012 15:29|
|Supervisor(s):||Mahapatra, K K|
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