Improved Techniques for High Performance Noise-Tolerant Domino CMOS Logic Circuits

Dhulipala, Srinivasa V S Sarma (2010) Improved Techniques for High Performance Noise-Tolerant Domino CMOS Logic Circuits. MTech thesis.



Domino CMOS logic circuit family finds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. However, there are inevitable problems that degrade the noise immunity of this family; they are the inevitable leakage current and the charge sharing. Added to the drawbacks is the relatively large power consumption, especially if compared to the static complementary CMOS logic family. To make the matter worse, these drawbacks are more tactile with the scaling of CMOS technology.
In my thesis, An introduction to domino logic, The impact of CMOS technology scaling on the performance of domino CMOS logic, Three Phase Domino Logic Circuit, High-performance noise-tolerant circuit techniques for CMOS dynamic logic and other Domino logic techniques are studied and corresponding Domino logic techniques have been designed and simulated. Specifically, the need to decrease the dynamic power consumption forces the designer to use a lower power-supply voltage. This in turn necessitates the reduction of threshold voltage to maintain the performance with the associated increase in sub threshold leakage current. So, a properly sized PMOS keeper must be used to compensate for this leakage. It will be found that the speed, which is the major advantage of domino logic compared to other logic styles, will degrade with CMOS technology scaling due to the contention current of the keeper. To assure high performance in noise tolerant techniques, the inevitable effects like leakage currents and charge distribution have to be minimized.
In this thesis few modifications have also been made to already existing domino techniques and different Domino logic circuits are simulated in both Cadence virtuoso (implemented using GPDK090- library of 90nm technology) and Mentor graphics (implemented at different technologies like Tsmc 035.mod, Tsmc 025.mod, Tsmc 018.mod) environments. The performance parameters are also compared with other standard architectures of Domino logic.

Item Type:Thesis (MTech)
Uncontrolled Keywords:Domino CMOS logic, CMOS technology scaling, speed, power consumption
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:4601
Deposited By:Ayas Swain
Deposited On:26 Sep 2013 15:55
Last Modified:26 Sep 2013 16:22
Supervisor(s):Mahapatra, K K

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