A Rigorous Simulation Based Study of Gate Misalignment Effects in Gate Engineered Double-Gate (DG) MOSFETs

Abstract

In this work, a numerical simulation based study on the effects of gate misalignment between the front and the back gate for gate engineered double-gate (DG) Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) has been presented. A comparative study of electrical characteristics and its effects on device performance between single material double gate (SMDG), double material double gate (DMDG) and triple material double gate (TMDG) MOSFETs have been investigated qualitatively. Both source side misalignment (SSM) and drain side misalignment (DSM) of different lengths in the back gate have been considered to investigate the effects of gate misalignment on device performance. In this context, an extensive simulation has been performed by a commercially available two-dimensional (2D) device simulator (ATLASTM, SILVACO Int.) to figure out the impacts of misalignment on device characteristics like surface potential, threshold voltage, drain-induced-barrier lowering (DIBL), subthreshold swing, subthreshold current, maximum drain current, transconductance and output conductance.