A soft error mitigation scheme to increase the resilience of register file

Dhulapelly, Madhuker (2013) A soft error mitigation scheme to increase the resilience of register file. MTech thesis.

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Abstract

Abstract Register files are essential and integral part of any microprocessor architecture. Soft errors in the register file can quickly spread to various parts of the system and result in silent data corruption. Traditional redundancy based schemes to protect the register file are prohibitive because register file is often in the timing critical path of the processor. Since it is one of the hottest blocks on the chip, adding any extra circuitry to it is not desirable. For embedded systems under severe cost constraints, where power, performance, area and reliability cannot be simply compromised, we propose a soft error reduction technique for register files. This thesis introduces a soft error mitigation scheme, called Self-Immunity to increase the resilience of the register file from soft errors, by using unused bits of the register file. It is desirable for processors that demand high register file integrity under stringent constraints. This thesis explains the implementation of our proposed technique to protect the register file from soft errors. And show the best overall results compared to state-of-the-art in register file vulnerability reduction with minimum impact on the area and power.

Item Type:Thesis (MTech)
Uncontrolled Keywords:Soft Errors, Register File,Register Vulnerability,Self Immunity
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:4628
Deposited By:Hemanta Biswal
Deposited On:22 Oct 2013 16:41
Last Modified:20 Dec 2013 11:14
Supervisor(s):Das, S K

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