Bhushan, Shiv (2013) An Analytical Model for the Threshold Voltage of Short-Channel Double-Material-Gate (DMG) MOSFETs with a Strained-Silicon (s-Si) Channel on Silicon-Germanium (SiGe) Substrates. MTech thesis.
As the silicon CMOS technology move into the sub-20nm regime, manufacturing limits and fundamental curb the traditional scaling of transistors. Modernization in device structures and materials will be needed for continued transistor miniaturization and equivalent performance improvements. Device dimensions are approaching their scaling limit giving rise to undesirable effects like short channel effects, gate leakage current, drain induced barrier lowering (DIBL) etc. Strained-silicon devices have been receiving enormous attention owing to their potential for achieving higher channel mobility and drive current enhancement and compatibility with conventional silicon processing.In this novel work, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon ( ) on silicon-germanium ( ) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson’s equation with suitable boundary conditions in both the strained-Si layer and relaxed layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations and also, the sub threshold swing is also analyzed for the device with different parameter variation. The model is used to investigate the excellent immunity against SCE offered by the DMG structure. The validity of the present 2D analytical model is verified with ATLASTM, a 2D device simulator from Silvaco Inc.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Double-material-gate,Hot Carrier Effect,Drain Induced Barrier Lowering,Strained-silicon on silicon-germanium MOSFETs|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Hemanta Biswal|
|Deposited On:||23 Oct 2013 14:11|
|Last Modified:||20 Dec 2013 15:17|
|Supervisor(s):||Tiwari, P K|
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