Design and FPGA Implementation of a Digital Signal Processor

Abstract

The project aims at designing a Digital Signal Processor with 32-bit ISA (Instruction Set Architecture) using Verilog HDL and the implementation of its components in FPGA (Field Programmable Gate Array). The processor is demonstrated using uniform 32- bit length instruction set containing instructions that are categorized into three formats, referred to as Register, Immediate and Jump type instructions. The project gives detailed description of design and simulation of the individual modules like the MAC, control module, arithmetic and logic unit, memory units, register file, program counter, data registers, muxes, ALU control, sign extender and the main module instantiating all formerly mentioned modules. For demonstration purposes, the processor is instructed to find the convolution of two input sequences, thus making use of all three instruction formats. After simulation, schematics generation and timing analysis is carried out in Xilinx ISE simulator. The individual modules are implemented and tested in Spartan 3E family XC3S500E FPGA board.