Sahoo, Bikash Chandra and Samant, Sanjay Kumar (2013) Design and power estimation of booth multiplier using different adder architectures. BTech thesis.
Modern IC Technology focuses on the design of ICs considering more area optimization and low power techniques. Multiplication is a heavily used arithmetic operation that figures prominently in signal processing and scientific applications. Multiplication is a very hardware intensive subject and we as users are mostly concerned with getting low-power,smaller area and higher speed.The most important concern in classic multiplication, mostly realized by K-cycles of shifting and adding, is to speed up underlying multi-operand addition of partial products. In this project we will present the design of Booth Multiplier with different adder architectures like Ripple Carry Adder & Carry Look Ahead Adder. The time delay, area and power have been analyzed for different adders. Also multipliers have been designed for both radix-2 and radix-4. Results will show the variation of area, speed and power for different designs. Also the power estimation method gives the deeper insight into power calculation and analysis. An approach have been suggested for peak power estimation.
|Item Type:||Thesis (BTech)|
|Uncontrolled Keywords:||Booth Multiplier;low-power;smaller area ;higher speed;radix-4;Scirocco and VirSim;Synopsys Design Compiler.|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Hemanta Biswal|
|Deposited On:||01 Nov 2013 11:43|
|Last Modified:||20 Dec 2013 15:02|
Repository Staff Only: item control page