Efficient router design for network on chip

S , Swapna (2013) Efficient router design for network on chip. MTech thesis.



A Network-on-chip (NoC) is a new paradigm in complex system-on-chip (SoC) designs that provide efficient on chip communication networks. It allows scalable communication and allows decoupling of communication and computation. The data is routed through the networks in terms of packets. The routing of data is mainly done by routers. So the architecture of router must be an efficient one with a lower latency and higher throughput. In this project we designed, implemented and analyzed three different router architectures for a network on chip communication. The routers have five ports, four ports connected to other ports in four different directions and the fifth port connected to the processing element through a network interface. The first architecture is a basic router with demultiplexer and scheduler. The second architecture consists of crossbar switch and arbiter. The third architecture uses the CDMA technology that is popular in wireless communication. The three architectures were analyzed for their performance in terms of delay, throughput and latency and we concluded that CDMA router performs better than the other two.

Item Type:Thesis (MTech)
Uncontrolled Keywords:Network on Chip; Router; CDMA; Crossbar; FPGA; Arbiter; Round Robin Scheduling
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:4912
Deposited By:Hemanta Biswal
Deposited On:06 Nov 2013 12:03
Last Modified:20 Dec 2013 09:42
Supervisor(s):Swain, A K

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