FPGE implementation of LDPC codes

Kumar, Abhishek (2013) FPGE implementation of LDPC codes. MTech thesis.



Low density parity check LDPC Code is a type of Block Error Correction code discovered and performance very close to Shanon’s limit .Good error correcting performance enables reliable communication. Since its discovery by Gallagar there is more research going on for its efficient construction and implementation. Though there is no unique method for constructing LDPC codes. Implementation of LDPC Code is done by taking different factors in to consideration such as error rate, parallelism of decoder, ease in implementation etc. This thesis is about FPGA implementation of LDPC codes and their performance evaluation. Protograph codes were introduced and analyzed by NASA's Jet Propulsion Laboratory in the early years of this century. Part of this thesis continues that work, investigating the decoding of specific protograph codes and extending existing tools for analyzing codes to protograph codes In this thesis I have taken the performance of LDPC coded BPSK modulated signal which is transmitted through AWGN channel and the performance is tested using MATLAB Simulation.

Item Type:Thesis (MTech)
Uncontrolled Keywords:FPGA implementation, LDPC, AR4JA, quasi cyclic encoding, sum product decoding algorithm
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:4983
Deposited By:Hemanta Biswal
Deposited On:05 Dec 2013 10:08
Last Modified:20 Dec 2013 11:43
Supervisor(s):Patra, S K

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