Low power encoder and comparator design of 5-bit flash ADC

Abstract

The present work of the thesis is divided into two parts, first is design of a low power encoder and second is low power latched comparator design. In this low power encoding scheme proposed for 4GS/s 5 bit flash analog to digital converter. The demanding issues in the design of a low power flash ADC is the design of thermometer code to binary code. An encoder in this thesis converts the thermo-meter code into binary code without any intermediate stage using dynamic CMOS logic. To decrease the power consumption of the Flash ADC, the implementation of encoder and comparator is done using dynamic CMOS logic. The proposed encoder in this thesis is designed using 90nm technology at 1.2V DC voltage source using CADENCE tool. The simulation results of 5-bit Flash ADC block is shown for a sampling frequency up to 4GHz and at 4GHz the encoder circuit showing the average power dissipation of the encoder block is 1.833 µW.The other part of the present work is the design of low power comparator for the 5-bit flash ADC. Dynamic latch comparator has been designed in order to reduce power dissipation, delays etc. The different parts of the dynamic latch comparator like: pre-amplifier, dynamic latch, and output buffer are implemented on CADENCE tool with 1.2 V power supply. The simulation results shown for a sampling frequency of 5 GHz and the average power dissipation of the proposed comparator is 69.09 µW. The physical layout of the encoder and comparator has been drawn using CADENCE VIRTUSO LAYOUT EDITOR. The DRC errors has been removed and the layout has been matched with the schematics.