Atlas based simulation study of junctionless double gate (DG) tunnel FET

Abstract

Tunnel Field Effect Transistor has recently attracted the attention of many researchers through its high Ion/Ioff ratio and a very less subthreshold slope. In this work Junction-less double gate tunnel field effect transistor’s performance has been studied which has been designed using charge plasma concept which can form the source and drain regions without the need for any doping by choosing appropriate work functions for the source and drain metal electrodes. A very important parameter of this device has been studied, i.e. the threshold voltage of this device. It has been seen that the variation of the threshold voltage with respect to the varying channel length of the device in almost nil. Also using it has been found that this device has a subthreshold slope of 56.7mV/decade with channel length of 50nm which is much lesser compared to the 60mV/decade subthreshold slope of a MOSFET, proving that this device can be used for switching performance in the future. Though the performance of the junction-less double gate TFET does not vary much compared to doped double gate Tunnel Field Effect Transistor, it is expected to be removed from all problems associated with random dopant fluctuations. Also its fabricating is possible on single crystal silicon-on-glass substrates which is formed by wafer scale epitaxial transfer.