Pati, G K (2014) Two dimensional analytical threshold voltage modeling of dual material gate S-SOI mosfet. BTech thesis.
MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is the one of the most important and widely used semiconductor devices used in industry for various proposes. Two most important advantages of MOSFETs are their extremely low power dissipation and small area required for fabrication, i.e high packing density .With the advance of technology the feature sizes of MOSFETs are reduced continuously to increase the packing density of very large scale integration (VLSI) circuits. With continuous shrinkage of device geometrics on threshold voltage causes strong deviations from long channel behavior. The effect of such decrease in channel length is called SCE (Short channel Effect). A two dimensional Poisson equation needs to be solved in order to understand the effect of SCE.SCE (Short Channel Effect) is the effect of reduction in the channel length of MOSFET which results in significant differences from ideal characteristic like channel length modulation, carrier velocity saturation, two dimensional charge sharing, drain induced barrier lowering (DIBL), drain source series resistance and punch through. In order to minimize the effect of short channel effect various different modeling has been introduced. Among them DG MOSFET (Double Gate MOSFET), SOI MOSFET (Silicon-On Insulator MOSFET) are particularly important. In this thesis, a two dimensional threshold voltage model is developed for a Dual Material Gate Fully Depleted Strained Silicon on Insulator (DMG-FD-S-SOI) MOSFET considering the interface trap charges. The interface trap charges during the pre and post fabrication process are a common phenomenon, and these charges can’t be neglected in nano scale devices. For finding out the surface potential, parabolic approximation is utilized to solve 2D Poisson’s equation in the channel region. Further, the virtual cathode potential method is used to formulate the threshold voltage.
|Item Type:||Thesis (BTech)|
|Uncontrolled Keywords:||Dual Material Gate DMG), interface trap charges, virtual cathode potential|
|Subjects:||Engineering and Technology > Electrical Engineering > Wireless Communication|
|Divisions:||Engineering and Technology > Department of Electrical Engineering|
|Deposited By:||Hemanta Biswal|
|Deposited On:||01 Aug 2014 16:24|
|Last Modified:||01 Aug 2014 16:24|
|Supervisor(s):||Sahu, P K|
Repository Staff Only: item control page