Mishra, Subhrajit and Dhar, Ishan (2007) Design of Timer for Application in ATM using FPGA and VHDL. BTech thesis.
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Abstract
A watchdog timer is a computer hardware timing device that triggers a system reset if the main program, due to some fault condition, such as a hang, neglects to regularly service the watchdog (writing a “service pulse” to it, also referred to as “petting the dog”). The intention is to bring the system back from the hung state into normal operation. Such a timer has got various important applications, one of them being in ATMs (Automated Teller Machine) which we have studied and designed in our project.
Item Type: | Thesis (BTech) |
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Uncontrolled Keywords: | VHDL, ATM, FPGA |
Subjects: | Engineering and Technology > Electronics and Communication Engineering > VLSI Engineering and Technology > Instrumentation |
Divisions: | Engineering and Technology > Department of Electronics and Communication Engineering |
ID Code: | 60 |
Deposited By: | Anshul Baranwal |
Deposited On: | 05 May 2009 15:20 |
Last Modified: | 05 May 2009 16:03 |
Supervisor(s): | Mahapatra, K K |
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