Roy, Achinta (2014) Design of 30-tap FIR filter using VHDL. BTech thesis.
A filter may be required to have a given frequency response, or a specific response to an impulse, step, or ramp, or simulate an analog system. Depending on the response of the system, digital filters can be classified into Finite Impulse Response (FIR) filters & Infinite Impulse Response (IIR) filters. The thesis deals with design of generic 30-tap FIR filter on FPGA. The thesis is focused on Design structure and occupied silicon space, needed for implementation of filter in FPGA. The results are IP macros of simple FIR filter that are full configurable using generic parameters. Both macros were verified in a verification environment which consists of test blocks (VHDL) and a comparative model (Matlab). A design of generic FIR filter is described in this work. Next there are described final designs of the IP macros, results and process of the verification, implementation and gate-level verification.
|Item Type:||Thesis (BTech)|
|Uncontrolled Keywords:||finite impulse,implementation,FPGA,IP macros,verification|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Hemanta Biswal|
|Deposited On:||25 Aug 2014 15:13|
|Last Modified:||25 Aug 2014 15:13|
|Supervisor(s):||Swain, A K|
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