Kumar, Gaurav (2014) Design of Frequency synthesizer. MTech thesis.
PLL frequency synthesizers play an important role in communication field and continuously increases. Frequency synthesizer is a system that generate a set of frequency, which is an integer multiple of input frequency. After that fractional frequency synthesizer was inventesd. In which output frequency is fractional multiple of input frequency. They suddenly used in mobile communication and in spread spectrum applications and their use continuously increasing. Communication used single carrier frequency, which is fixed. After modulation when modulating signal transmitted, then frequency of modulating signal will change because of noise. So at receiver to get the input signal, we require input carrier frequency so that we require frequency synthesizer. PLL is closed loop frequency system that can be used as a frequency synthesizer and for synchronizing purpose. PLL’s are having building block like, Phase frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO). When it used as a frequency synthesizer than one another block require which is called divider circuit. PFD compare input signal frequency and phase with feedback signal and generate UP and DOWN signal. Which drive charge pump, that convert two signal into one signal. That signal increase or decrease the charge of loop filter. By which output frequency of VCO will change, it may be increase or decrease depending on charge on loop filter. That output frequency (fvco) applied to divider circuit, which divide the f vco by an number, that number may be integer or fractional. Output frequency of divider circuit compare with input frequency. If input frequency same as feedback frequency and phase error is zero then we say that PLL is locked, mean’s frequency of input signal same as feedback signal and phase difference between is zero. After locked state, output of PFD is zero and charge on loop filter also constant, so fvco is constant. After that PLL track the input signal.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||CP;VCO;PFD;Phase noise;Divider circuit|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Hemanta Biswal|
|Deposited On:||25 Aug 2014 16:04|
|Last Modified:||25 Aug 2014 16:04|
|Supervisor(s):||Acharya, D P|
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