S P, Deepu (2014) Low Power Thermometer code to Binary code Encoder based Flash ADC. MTech thesis.
Architectural level design of a low power Thermometer code to Binary code Encoder for a Flash ADC of 4 bit resolution is presented. In the proposed architecture the thermometer code is initially converted into intermediate gray code using 2:1 multiplexers and then to the binary code using XOR gates. Various logic styles (CMOS, Transmission gate logic, DPL, CPL, EEPL, LEAP, SRPL, PPL) are studied for the design of 2:1 Multiplexers and XOR gate. The performance of proposed architecture is compared with other available architectures like multiplexer based direct conversion method, wallace tree encoder, intermediate gray code based encoder using basic gates and using 2:1 multiplexers. From the study it is obtained that the proposed architecture consumes lesser power and gives a comparable delay performance (only direct conversion using 2:1 multiplexers gives better delay performance). The proposed architecture uses minimum number of multiplexers for the conversion and consumes 25.64µW of power with a power supply of 1.8V. A 4 bit flash ADC is designed using the proposed encoder in Cadence UMC 0.18µm technology and the working is verified.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Thermometer code to binary Code Encoder; Analog to Digital Converter; Flash ADC; Low Power VLSI Design; Comparators;|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Hemanta Biswal|
|Deposited On:||25 Aug 2014 16:27|
|Last Modified:||25 Aug 2014 16:27|
|Supervisor(s):||Islam, M N|
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