Design of Address Decoder and Sense Amplifier for SRAM

Abstract

Address decoder and sense amplifier is important component of SRAM memory. Selection of storage cell and read operation is depends on decoder and sense amplifier respectively. Hence, performance of SRAM is depends on these components. This work survey the address decoder and sense amplifier for SRAM memory, concentrating on delay optimization and power efficient circuit techniques. We have concentrated on optimal decoder structure with least number of transistors to reduce area of SRAM In static decoders we have stared with simple AND gate decoder and its result is examined. These simple decoder are neither area efficient nor faster one because AND/OR gate are not natural gates, they are made up from combination of NAND/NOR and NOT gate. Decoder having only NOR/NAND gate are area efficient and fast too. Therefore universal decoding having NAND-NOR alternate stages scheme is taken and examined. Universal decoding scheme are having some serious issue like different path delay which may results in false decoding as well as extra power dissipation. To overcome from this issue Novel Address decoding scheme is implemented and their result is compared with simple AND decoder and Universal decoder. Novel address decoder circuit is presented and analyzed. Novel address decoder using NAND-NOR alternate stages with pre-decoder and replica inverter chain circuit is implemented successfully. Current mirror sense-amp and latched type sense amplifier is also implemented for SRAM. These two amplifiers are the basic one and having tremendous advantage due to their small size. They are fast enough and can be fit below the SRAM cell. We have implemented and tested 1Kb; 8 bit; 1.25GHz SRAM memory in Cadence by using UMC 90nm technology, for that decoder and sense amplifier is deployed.