Tiwari, A (2014) Performance comparison of cache coherence protocol on multi-core architecture. MTech thesis.
Number of cores in multi-core processors is steadily increased to make it faster and more reliable. Increasing the number of cores comes with a numerous issues that need to be addressed. In this dissertation we looked at the cache coherence issue, its importance and solution. Cache coherence is important as two or more cores sharing the same data must maintain the recent updated value to avoid reading of stale value. We have made an extensive study of existing cache coherence methods, such as Snoopy coherence technique and Directory coherence technique. Snoopy coherence technique is studied with the help of MOESI coherence protocol and Directory coherence technique is observed with the help of MI, MESI TWO LEVEL, MESI THREE LEVEL, MOESI, and MOESI TOKEN coherence protocol. We have used GEM5 simulator and Splash-2 benchmark to compare their performance. For simulation a precompiled program called MemTest, Ruby random tester, and Splash-2 suite is used. It is observed that the performance is improved as we move from MI, MESI TWO LEVEL, MESI THREE LEVEL, MOESI, and MOESI TOKEN in Directory coherence technique and for Snoopy coherence we observed the performance through varying parameters like, cache size, block size and associativity. It is also observed that that adding L3 level cache the performance of MESI Three Level is improved over MESI Two Level.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Multi-core processors, Cache Coherence, Snoopy Coherence technique, Directory Coherence technique.|
|Subjects:||Engineering and Technology > Computer and Information Science|
|Divisions:||Engineering and Technology > Department of Computer Science|
|Deposited By:||Hemanta Biswal|
|Deposited On:||28 Aug 2014 11:35|
|Last Modified:||28 Aug 2014 11:35|
|Supervisor(s):||Turuk, A K|
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