Performance analysis of Dual Material Gate (DMG) Silicon on Insulator (SOI) tunnel fets

Abstract

As modern day computing systems are designed to perform innumerable number of functions with tremendous speed, the number of circuits to be accommodated in a chip keeps increasing day by day. Hence electronics industry constantly faces the challenge of miniaturization of transistors to increase the package density and thus linear scaling of CMOS technology has become a necessity in the present day microelectronic and nano-electronic regime. This leads to a major crisis of static power consumption and hence conventional MOSFETs fail to be a suitable candidate to handle the situation. Also Short Channel Effects(SCEs) come into picture. So non-conventional devices started gaining its significance to meet the ITRS requirements. A promising candidate that attracted attention was Tunnel FETs which are gated reverse biased p-i-n diodes where ON current would be due to band-to-band tunneling and they exhibit very low OFF current of 10-17 A/µm which makes them a potential solution for power crisis. Also they prove to be an energy efficient electronic switch with a subthreshold swing not limited to 60mV/decade. Negligible Short Channel Effects of these devices gives them an added advantage over conventional MOSFETs .All these features raise up Tunnel FET as superior candidate for future CMOS era. In the presented work, an analysis into the performance of a Dual Material Gate Single Dielectric SOI Tunnel FET has been done. Numerous simulations were done to determine the influence of work functions of both the gate materials on the electrical characteristics of the device. Comparative study was done between Dual Material Gate device and Single Material Gate device with regards to their electrical characteristics as well as SCEs like Drain Induced Barrier Lowering(DIBL) and threshold voltage roll-off. Parameters like intrinsic capacitances as well as transconductances were also determined.