Efficient Architecture by Effective Floorplanning of Cores in Processors

Abstract

Hotspots in cores are becoming more prominent all thanks to the increasing clock speed in the market. Core size cannot be increased further. Better technology means reducing the heat or distributing the heat evenly to keep the peak temperature low. One has to find a trade-off between area and cost to make the cores and overall architecture cost effective and heat controlled. Generating floorplans and evaluating them to make the best core is underway. For the current market a trade-off has to be made between area and peak temperature. The floorplan accepted can be built into the desired architecture to gain efficient results.