Memory chip design using cadence

Sahoo, Debasish (2014) Memory chip design using cadence. BTech thesis.



In this paper an effort is made to design 16 bit SRAM memory array on 180nm technology. For high-speed memory applications such as cache, a SRAM is often used. Access time, speed, and power consumption are the three key parameters for an SRAM memory design (SRAM). The integrated SRAM is operated with analog input voltage of 0 to 1.8v. The 16 bit SRAM memory has been designed, implemented &analysed in standard UMC180nm technology library using Cadence tool.We alsoanalyse the read and write operation of the designed memory cell.

Item Type:Thesis (BTech)
Uncontrolled Keywords:SRAM cell;Precharge;Driver circuit; sense amplifier;decoder;cadence;UMC
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:6373
Deposited By:Hemanta Biswal
Deposited On:10 Sep 2014 09:50
Last Modified:10 Sep 2014 09:50
Supervisor(s):Acharya, D P

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