Memory chip design using cadence

Abstract

In this paper an effort is made to design 16 bit SRAM memory array on 180nm technology. For high-speed memory applications such as cache, a SRAM is often used. Access time, speed, and power consumption are the three key parameters for an SRAM memory design (SRAM). The integrated SRAM is operated with analog input voltage of 0 to 1.8v. The 16 bit SRAM memory has been designed, implemented &analysed in standard UMC180nm technology library using Cadence tool.We alsoanalyse the read and write operation of the designed memory cell.