Low-power OP-AMP operating in sub-threshold region with improved slew rate

Abstract

This thesis focuses on the weak inversion design of low power low voltage Op-amp. The main objective of this thesis is to improve the slew rate of the Op-amp with a very less amount of power consumption. For this purpose, an adaptive bias circuit is used to improve the slew rate of an Op-amp in sub-threshold region by increasing the drain current of the input stage transistor of Op-amp under the dynamic condition instead increasing the quiescent current to reduce the power consumption. In this thesis we present sub-threshold Op-amp circuit with two different adaptive bias topology. First, an adaptive biased circuit with WTA (Winner Take All) topology, which is used in a class A Op-amp circuit and this circuit designed using UMC 180nm technology with a supply voltage of 0.8V. The second one is an adaptive bias circuit based on current subtractor topology, this topology is used in a class AB Op-amp circuit with supply voltage of ±0.6V. This thesis presents the comparison between Op-amp with adaptive bias (both topology) and without adaptive bias circuit.